Leandro Barbosa Lima1, Yuzo Iano2
Doutorando em Engenharia Elétrica e Computação1, Doutor em Engenharia Elétrica2
ABSTRACT: WHEN DEVELOPING A NEW SYSTEM, IT IS IMPORTANT TO VERIFY THAT THE SYSTEM COMPLIES WITH DOCUMENTED REQUIREMENTS AND PROVIDES SPECIFIC FEATURES. THEREFORE, DESIGN AND VERIFICATION, COMMONLY KNOWN AS FRONT-END IN THE DIGITAL INTEGRATED CIRCUIT DESIGN FLOW, FOCUSES MAXIMUM ATTENTION ON THIS DESIGN PHASE IN ORDER TO GUARANTEE THE FUNCTIONALITY OF THE DEVICE IN A SAFE MANNER. BY SECURELY GUARANTEEING SYSTEM FUNCTIONALITY, THROUGH THE IMPLEMENTATION OF FUNCTIONAL VIRIFICATION COMPONENTS FOR “FUNCTIONAL VERIFICATION” VALIDATION, THE ERM METHODOLOGY (E-LANGUAGE REUSE METHODOLOGY) IS USED TO GENERATE STIMULI IN THE AES (ENCRYPTION STANDARD ADVANCE) DEVICE. VERIFICATION IS PERFORMED IN THE AES DIGITAL DEVICE THAT IS IMPLEMENTED IN HDL (HARDWARE DESCRIPTION LANGUAGE) VERILOG. IT HAS THE FUNCTIONALITY OF ENCRYPTING AND DECRYPTING TEXTS, AND CAN GENERATE KEYS WITH A SIZE OF 128 BITS. IN ORDER TO ENSURE THE FUNCTIONALITY OF THE DEVICE, THE CODE COVERAGE FEATURE WAS ALSO USED. THERE ARE MANY ADVANTAGES IN USING SUCH A FEATURE IN DESIGN, AND IT CAN BE USED IN FUNCTIONAL VERIFICATION THROUGH SVA ASSERTIONS, AS THEY ARE NATIVELY INTEGRATED INTO THE LANGUAGE IN THE SYSTEM VERYLOG LANGUAGE, CAN BE VERIFIED IN SIMULATION AND FORMAL VERIFICATION, AND ARE CONVENIENT FOR DESIGNERS TO USE DURING CODING.
KEYWORDS: AES, ENCRYPTION, HDL, HARDWARE SECURITY, FUNCTIONAL VERIFICATION, VERILOG.
